Integrated circuits and other semiconductor and electronic products are routinely tested to ensure that they function properly before a product containing the device under test (DUT) is shipped, sold, or placed into use. Automatic test pattern generation (ATPG) systems are used to generate a set of test patterns that will efficiently test for and detect faults on the tested device. ATPG systems use a model of a device to formulate the test patterns, test vectors, etc. that may be used by automatic testing equipment (ATE) to test the DUT.
A variety of automatic test equipment (ATE) have long been known for testing electronic circuits, devices, integrated circuits, and other semiconductor and electronic products. Generally, automatic test equipment is divided into two broad categories, analog testers and digital testers. As the names imply, analog testers are generally designed for testing analog circuit devices, while digital testers are designed for testing digital circuit devices. Digital testers generally include a testing device having a number of internal circuit cards or channels that generate programmably controlled test signals for testing and evaluating a DUT. More specifically, ATE may be programmably controlled to be adapted or configured to test a variety of devices in a variety of ways. This is achieved by programming ATE inputs to inject a certain signal (or signal transition) and by programming ATE outputs to compare a value to a certain pin or signal line on a DUT. In this regard, a digital tester generally includes a test head by which electrical signals are input to and output from the tester. The test head comprises a number of connectors, each defining a channel, which may be connected via cable or otherwise to a device under test. The electronics within the digital tester may then input and output signals to/from a DUT via the test head.
By way of an extremely simple illustration, consider a digital tester that is configured to test a package containing, among other things, a two input AND gate. The digital tester may be configured to apply a logic one on the two signal lines that correspond to the inputs of the AND gate, then receive the signal on the signal line corresponding to the output to ensure that it is driven to a logic one in response. The tester may then be configured to alternatively apply logic zero signals on each of the two signal lines corresponding to the AND gate inputs, in order to verify that the output of the AND gate transitions from a logic one to a logic zero in response. If proper (i.e., expected) operation is not realized, then a defect is detected.
An integrated circuit tester includes a set of channels or “nodes”, wherein one node is associated with each terminal of the DUT. When the DUT is an integrated circuit chip (IC) chip, then one channel may be associated with each pin of the IC chip. A test is organized into a set of successive time segments (“test cycles”). During any given test cycle, each channel can either transmit a test signal to the pin, sample a DUT output signal at the associated pin, or do neither. Each channel includes its own memory for storing a sequence of these transmit or sample commands (“test vectors”).
As known in the art, an ATPG system is independent and distinct from a tester. An ATPG system uses a model of a DUT to formulate a set of test vectors that will efficiently test for and detect faults on the tested device. Whereas, a tester is a device disposed downstream of the test generator. It utilizes the set of test vectors generated by the test generator in order to test the actual device.
Existing ATPG solutions, however, may be problematic due to the amount of required processing time, resources, etc. Typically, during existing ATPG processes, the device model is flattened (i.e., all levels of hierarchy are removed). Then, an ATPG algorithm designates (for the entire device model) whether the particular fault being tested may be detected (i.e., whether a test pattern can be generated to detect the fault). In this regard, an ATPG algorithm typically designates a so-called fault status for each fault in the design model (e.g., “untestable fault,” “undetected fault,” “detected fault,” etc.). During ATPG processing, if a test pattern is generated, the fault may be categorized as “detected.” For instance, if the ATPG algorithm cannot generate a test pattern after all possibilities have been exhausted, the fault may be categorized as “untestable.” An ATPG algorithm may also implement an abort limit in order to manage processing resources. In this manner, a fault may be categorized as “undetected” if the abort limit is reached before the ATPG algorithm is able to resolve the fault as “detected” or “untestable.” If ATPG processing terminates in this way, fault coverage may be hindered because the ATPG algorithm could have generated a pattern but did not. Existing solutions require substantial processing time, resources, etc. to detect faults and/or to determine that a fault is untestable.